1. Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
【提示】没把singal放到process（）中。
2.Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
【提示】是说设计中没有对时钟进行约束。【解决】在assignment/timing anlaysis setting/inipidual clock中设置
3. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
【提示】设计中出现门控时钟问题，最好修掉，时钟分析会更容易通过，系统更稳。如果是必须的，可以忽略此提示。
4. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.
【提示】电路设计里面出现了组合逻辑信号反馈的一个闭环。这样没有经过寄存器的反馈会造成电路很不稳定，很容易出现毛刺。建议修改。
5. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
【提示】寄存器没有接时钟。
6. Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
【提示】寄存器没有赋值，软件自动将输入接GND。
7.Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "USB_SLOE" is stuck at VCC
【提示】输出信号连接到固定值，如果是实际情况可以忽略，不是的话就去看看原因吧。
8.Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
【提示】top层有些管脚没有绑定到FPGA pin上面。仔细找找吧。
9.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
【提示】PLL的相位没有设置或默认为0.确实不需设置的时候可以忽略。
10.Warning：“xxxx” used but never defined...
【提示】XXX信号已经使用但是没有定义，这个一定要定义的哦。
11.Warning：“xxxx” defined but never used...
【提示】XXX信号已经定义但是没有使用，这个可以忽略。但是要问问自己问什么定义呢？
12.Can't analyze file -- file E://quartusii/*/*.v is missing
原因：试图编译一个不存在的文件，该文件可能被改名或者删除了
措施：不管他，没什么影响
13.Warning: Can't find signal in vector source file for input pin
|whole|clk10m
原因：因为你的波形仿真文件（ vector source file ）中并没有把所有的输入
信号(input pin)加进去，对于每一个输入都需要有激励源的