==========================================================================//-----------------------------------------------------// Design Name : Uart // File Name : Uart.V// Function : Simple UART// Coder : Deepak Kumar Tala//-----------------------------------------------------Module Uart (Reset ,Txclk ,Ld_tx_data ,Tx_data ,Tx_enable ,Tx_out ,Tx_empty ,Rxclk ,Uld_rx_data ,Rx_data ,Rx_enable ,Rx_in ,Rx_empty);// Port DeclarationsInput Reset ;Input Txclk ;Input Ld_tx_data ;Input [7:0] Tx_data ;Input Tx_enable ;Output Tx_out ;Output Tx_empty ;Input Rxclk ;Input Uld_rx_data ;Output [7:0] Rx_data ;Input Rx_enable ;Input Rx_in ;Output Rx_empty ;// Internal Variables Reg [7:0] Tx_reg ;Reg Tx_empty ;Reg Tx_over_run ;Reg [3:0] Tx_cnt ;Reg Tx_out ;Reg [7:0] Rx_reg ;Reg [7:0] Rx_data ;Reg [3:0] Rx_sample_cnt ;Reg [3:0] Rx_cnt ; Reg Rx_frame_err ;Reg Rx_over_run ;Reg Rx_empty ;Reg Rx_d1 ;Reg Rx_d2 ;Reg Rx_busy ;// UART RX LogicAlways @ (Posedge Rxclk Or Posedge Reset)If (Reset) BeginRx_reg <= 0; Rx_data <= 0;Rx_sample_cnt <= 0;Rx_cnt <= 0;Rx_frame_err <= 0;Rx_over_run <= 0;Rx_empty <= 1;Rx_d1 <= 1;Rx_d2 <= 1;Rx_busy <= 0;End Else Begin// Synchronize The Asynch SignalRx_d1 <= Rx_in;Rx_d2 <= Rx_d1;// Uload The Rx DataIf (Uld_rx_data) Begin Rx_data <= Rx_reg; Rx_empty <= 1;End// Receive Data Only When Rx Is EnabledIf (Rx_enable) Begin // Check If Just Received Start Of Frame If (!Rx_busy && !Rx_d2) Begin Rx_busy <= 1; Rx_sample_cnt <= 1; Rx_cnt <= 0; End // Start Of Frame Detected, Proceed With Rest Of Data If (Rx_busy) Begin Rx_sample_cnt <= Rx_sample_cnt + 1; // Logic To Sample At Middle Of Data If (Rx_sample_cnt == 7) Begin If ((Rx_d2 == 1) && (Rx_cnt == 0)) Begin Rx_busy <= 0; End Else Begin Rx_cnt <= Rx_cnt + 1; // Start Storing The Rx Data If (Rx_cnt > 0 && Rx_cnt < 9) Begin Rx_reg[Rx_cnt - 1] <= Rx_d2; End If (Rx_cnt == 9) Begin Rx_busy <= 0; // Check If End Of Frame Received Correctly If (Rx_d2 == 0) Begin Rx_frame_err <= 1; End Else Begin Rx_empty <= 0; Rx_frame_err <= 0; // Check If Last Rx Data Was Not Unloaded, Rx_over_run <= (Rx_empty) ? 0 : 1; End End End End End EndIf (!Rx_enable) Begin Rx_busy <= 0;EndEnd// UART TX LogicAlways @ (Posedge Txclk Or Posedge Reset)If (Reset) BeginTx_reg <= 0;Tx_empty <= 1;Tx_over_run <= 0;Tx_out <= 1;Tx_cnt <= 0;End Else Begin If (Ld_tx_data) Begin If (!Tx_empty) Begin Tx_over_run <= 0; End Else Begin Tx_reg <= Tx_data; Tx_empty <= 0; End End If (Tx_enable && !Tx_empty) Begin Tx_cnt <= Tx_cnt + 1; If (Tx_cnt == 0) Begin Tx_out <= 0; End If (Tx_cnt > 0 && Tx_cnt < 9) Begin Tx_out <= Tx_reg[Tx_cnt -1]; End If (Tx_cnt == 9) Begin Tx_out <= 1; Tx_cnt <= 0; Tx_empty <= 1; End End If (!Tx_enable) Begin Tx_cnt <= 0; EndEndEndmodule
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