1. Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
【提示】没把singal放到process（）中。
2.Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
【提示】是说设计中没有对时钟进行约束。【解决】在assignment/timing anlaysis setting/inipidual clock中设置
3. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
【提示】设计中出现门控时钟问题，最好修掉，时钟分析会更容易通过，系统更稳。如果是必须的，可以忽略此提示。
4. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.
【提示】电路设计里面出现了组合逻辑信号反馈的一个闭环。这样没有经过寄存器的反馈会造成电路很不稳定，很容易出现毛刺。建议修改。
5. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
【提示】寄存器没有接时钟。
6. Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
【提示】寄存器没有赋值，软件自动将输入接GND。