阻塞赋值的执行可以认为是只有一个步骤的操作，即计算RHS并更新LHS，且不允许其他语句的干扰。
非阻塞赋值可以看做两个步骤的过程：
1. 在赋值时刻开始时，计算非阻塞赋值RHS表达式；2. 在赋值时刻结束时，更新非阻塞赋值LHS表达式。RHS-方程式右手方向的表达式或变量；LHS-方程式左手方向的表达式或变量。module k(clk,x,k);
input x,clk;
output k;
reg k;
reg y,z;always @(posedge clk) begin
y = x;
z = y;
k = z;
end
endmodule很明显，用阻塞赋值，就相当于把x，y，z用一根线连在一起，最后的结果就相当于x给k赋值。倘若用非阻塞赋值module k(clk,x,k);
input x,clk;
output k;
reg k;
reg y,z;always @(posedge clk) begin
y <= x;
z <= y;
k <= z;
end
endmodule这个就是用非阻塞赋值实现的移位寄存器。再举个例子module count(clk,count1,count2,count3,count4);
input clk;
output [3:0]count1,count2,count3,count4;
reg [3:0]count1 = 0,count2 = 0,count3 = 0,count4 = 0 ;always @(posedge clk) begin
if(count1 == 4)
count1 <= 0;
else
count1 <= count1 + 1;endalways @(posedge clk) begin
count2 <= count2 + 1;
if(count2 == 4)
count2 <= 0;
endalways @(posedge clk) begin
if(count3 == 4)
count3 = 0;
else
count3 = count3 + 1;
endalways @(posedge clk) begin
count4 = count4 + 1;
if(count4 == 4)
count4 =0;
end再举个例子module time1(clk,CLK,anter);input clk;output CLK;output [3:0]anter;reg CLK;reg [3:0]anter;always @(posedge clk) begin if(anter < 8) anter = anter + 1; else anter = 0; if(anter < 5) CLK = 1'b1; elseCLK = 1'b0;endendmodule仿真结果如下
module time1(clk,CLK,anter);
input clk;output CLK;output [3:0]anter;reg CLK;reg [3:0]anter;always @(posedge clk) begin if(anter < 8) anter <= anter + 1; else anter <= 0; if(anter < 5) CLK = 1'b1; elseCLK = 1'b0;endendmodule
以上就是所有的例子，多看些例子对比，应该就比较清楚明了了。