TI2000系列的头文件直接调用

;*************************************************************; File Name:      x24x.h; Description: x24x Peripheral Registers + other useful definitions; Target:       x240/3, x/2407;====================================================================;; Select the target device by setting 1;--------------------------------------------------------------x240  .set 0 ; C/F240x243  .set 1 ; C/F243x2407  .set 0 ; F2407;For F2407EVM only;Select PLL multiplication ratiox2_PLL .set 1x4_PLL .set 0;--------------------------------------------------------------; On Chip Periperal Register Definitions;--------------------------------------------------------------;C2xx Core RegistersIMR  .set 0004h  ; Int MaskGREG  .set 0005h  ; Global memory allocationIFR  .set 0006h  ; Int FlagABRPT  .set 01fh  ; Analysis BreakPointWSGR  .set 0FFFFh      ; Wait State Control (IO space mapped);System Module RegistersPIRQR0 .set 7010h  ; Peripheral Interrupt Request Reg0(241/2/3,240x only)PIRQR1 .set 7011h  ; Peripheral Interrupt Request Reg1(241/2/3,240x only)PIRQR2 .set 7012h  ; Peripheral Interrupt Request Reg2(240x)SYSCR  .set 7018h  ; System Control (X240 only)SYSSR  .set 701Ah  ; System Status (X240 only)SYSIVR .set  701Eh  ; System Int Vector (X240 only)SSCR  .set  7018h  ; System Stat & Contr (X241/2/3 only)PIVR  .set  701Eh  ; Periph Int Vector (X241/2/3 only)SCSR1  .set 07018h      ; System contr & stat 1 (240x only)SCSR2  .set 07019h      ; System contr & stat 2 (240x only)DIN  .set 0701Ch      ; Device Identification Register; External interrupt configuration registersXINT1CR240 .set  7070h ; Int1 (type A) config (X240 only)XINT2CR240 .set  7078h ; Int2 (type C) config (X240 only)XINT3CR240 .set  707Ah ; Int3 (type C) config (X240 only)NMICR       .set  7072h ; NMI (type A) config (X240 only)XINT1CR .set  7070h  ; Int1 config. X241/2/3, (X240x only)XINT2CR .set  7071h  ; Int2 config. X241/2/3, (X240x only)XINT1_CNTL .set 07070h ;Int1 (type A) Control regNMI_CNTL      .set 07072h ;Non maskable Int (type A) Control regXINT2_CNTL .set 07078h ;Int2 (type C) Control regXINT3_CNTL .set 0707Ah ;Int3 (type C) Control reg; PLL configuration registers - X240 onlyCKCR0  .set  702ah  ; PLL Clock Control 0 (X240 only)CKCR1  .set  702ch  ; PLL Clock Control 1 (X240 only);Digital I/OOCRA  .set 07090h      ; Output Control AMCRA  .set 07090h  ;I/O Mux Control Reg AOCRB  .set 07092h      ; Output Control BMCRB  .set 07092h  ;I/O Mux Control Reg BOCRC  .set 07094h      ; Output control C (X240x only)ISRA   .set  7094h  ; Input Status A (X240 only)ISRB   .set  7096h  ; Input Status B (X240 only)IPSRA  .set 07094h  ;Input Status Reg AIPSRB  .set 07096h  ;Input Status Reg BPADATDIR .set 07098h      ; I/O port A Data & DirectionPBDATDIR .set 0709Ah      ; I/O port B Data & DirectionPCDATDIR .set 0709Ch      ; I/O port C Data & DirectionPDDATDIR .set 0709Eh  ;I/O port D Data & Direction reg.PEDATDIR .set 07095h   ; I/O port D Data & DirectionPFDATDIR .set 07096h   ; I/O port D Data & Direction;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) RegistersRTI_CNTR .set 07021h   ; RTI Counter regWD_CNTR  .set 07023h   ; WD Counter regWD_KEY .set 07025h   ; WD Key regWDKEY  .set WD_KEYRTI_CNTL .set 07027h   ; RTI Control regWD_CNTL  .set 07029h   ; WD Control regWDCR  .set WD_CNTLPLL_CNTL1 .set 0702Bh   ; PLL control reg 1PLL_CNTL2 .set 0702Dh   ; PLL control reg 2;Analog-to-Digital Converter(ADC) registers - x240/1/2/3ADC_CNTL1 .set 07032h   ; ADC Control reg 1ADC_CNTL2 .set 07034h   ; ADC Control reg 2ADC_FIFO1 .set 07036h   ; ADC FIFO data reg 1ADC_FIFO2 .set 07038h   ; ADC FIFO data reg 2ADCTRL1 .set 07032h   ; ADC Control reg 1ADCTRL2 .set 07034h   ; ADC Control reg 2ADCFIFO1 .set 07036h   ; ADC FIFO data reg 1ADCFIFO2 .set 07038h   ; ADC FIFO data reg 2;--------------------------------------------------------------; ADC Register declarations - x240x;--------------------------------------------------------------ADCL_CNTL1  .set 070A0h ;ADC Control reg 1ADCL_CNTL2  .set 070A1h ;ADC Control reg 2MAXCONV  .set 070A2h ;Maximum conversions in sequenceCHSELSEQ1  .set 070A3h ;Channel select fields: Results 3,2,1,0CHSELSEQ2  .set 070A4h ;Channel select fields: Results 7,6,5,4CHSELSEQ3  .set 070A5h ;Channel select fields: Results 11,10,9,8CHSELSEQ4  .set 070A6h ;Channel select fields: Results 15,14,13,12AUTO_SEQ_SR  .set 070A7h ;Auto-sequence status RegisterADC_RESULT0  .set 070A8h ;Conversion result 0ADC_RESULT1  .set 070A9h ;Conversion result 1ADC_RESULT2  .set 070AAh ;Conversion result 2ADC_RESULT3  .set 070ABh ;Conversion result 3ADC_RESULT4  .set 070ACh ;Conversion result 4ADC_RESULT5  .set 070ADh ;Conversion result 5ADC_RESULT6  .set 070AEh ;Conversion result 6ADC_RESULT7  .set 070AFh ;Conversion result 7ADC_RESULT8  .set 070B0h ;Conversion result 8ADC_RESULT9  .set 070B1h ;Conversion result 9ADC_RESULT10 .set 070B2h ;Conversion result 10ADC_RESULT11 .set 070B3h ;Conversion result 11ADC_RESULT12 .set 070B4h ;Conversion result 12ADC_RESULT13 .set 070B5h ;Conversion result 13ADC_RESULT14 .set 070B6h ;Conversion result 14ADC_RESULT15 .set 070B7h ;Conversion result 15CALIBRATION  .set 070B8h ;Calibration Register;Serial Peripheral Interface (SPI) RegistersSPI_CCR  .set 07040h ;SPI Config Control Reg 1SPI_CTL  .set 07041h ;SPI Operation Control Reg 2SPI_STS  .set 07042h ;SPI Status RegSPI_BRR  .set 07044h ;SPI Baud rate control regSPI_EMU  .set 07046h ;SPI Emulation buffer regSPI_BUF  .set 07047h ;SPI Serial Input buffer regSPI_DAT  .set 07049h ;SPI Serial Data regSPI_PC1  .set 0704Dh ;SPI Port control reg1SPI_PC2  .set 0704Eh ;SPI Port control reg2SPI_PRI  .set 0704Fh ;SPI Priority control reg;Serial Communications Interface (SCI) RegistersSCI_CCNTL .set 07050h ;SCI Comms Control RegSCI_CNTL1 .set 07051h ;SCI Control Reg 1SCI_HBAUD .set 07052h ;SCI Baud rate controlSCI_LBAUD .set 07053h ;SCI Baud rate controlSCI_CNTL2 .set 07054h ;SCI Control Reg 2SCI_RX_STAT .set 07055h ;SCI Receive status regSCI_RX_EMU .set 07056h ;SCI EMU data bufferSCI_RX_BUF .set 07057h ;SCI Receive data bufferSCI_TX_BUF .set 07059h ;SCI Transmit data bufferSCI_PORT_C1 .set 0705Dh ;SCI Port control reg1SCI_PORT_C2 .set 0705Eh ;SCI Port control reg2SCI_PRI       .set 0705Fh ;SCI Priority control reg;Event Manager (EV)/Event Manager A (EVA) RegistersGPTCON .set 07400h ; General Timer ControlT1CNT  .set 07401h ; T1 CounterT1CMP  .set 07402h ; T1 Compare valueT1PR  .set 07403h ; T1 PeriodT1CON  .set 07404h ; T1 ControlT2CNT  .set 07405h ; T2 CounterT2CMP  .set 07406h ; T2 Compare valueT2PR  .set 07407h ; T2 PeriodT2CON  .set 07408h ; T2 ControlT3CNT  .set 07409h ; T3 Counter (240 Only)T3CMP  .set 0740ah ; T3 Compare (240 Only)T3PR  .set 0740bh ; T3 Period (240 Only)T3CON  .set 0740ch ; T3 Control (240 Only)COMCON .set 07411h ; Compare ControlACTR  .set 07413h ; Compare Output Action Control (240 Only)SACTR  .set 07414h ; S Comp Output Action Control (240 Only)DBTCON .set 07415h ; Dead Band ControlCMPR1  .set 07417h ; Compare value 1CMPR2  .set 07418h ; Compare value 2CMPR3  .set 07419h ; Compare value 3SCMPR1 .set 0741ah ; S Comp value 1 (240 Only)SCMPR2 .set 0741bh ; S Comp value 2 (240 Only)SCMPR3 .set 0741ch ; S Comp value 3 (240 Only)CAPCON .set 07420h ; Capture ControlCAPCONA .set 07420h ; Capture ControlCAPFIFO  .set 07422h ; Capture FIFO1-3/4 StatusFIFO1  .set 07423h ; Capture 1 FIFO TopFIFO2  .set 07424h ; Capture 2 FIFO TopFIFO3  .set 07425h ; Capture 3 FIFO TopFIFO4  .set 07426h ; Capture 4 FIFO Top (240 Only)FIFOBT1 .set 07427h ; Capture 1 FIFO Bottom (240x only)FIFOBT2 .set 07428h ; Capture 2 FIFO Bottom (240x only)FIFOBT3 .set 07429h ; Capture 3 FIFO Bottom (240x only)IMRA  .set 0742ch ; Group A Int MaskIMRB  .set 0742dh ; Group B Int MaskIMRC  .set 0742eh ; Group C Int MaskEVIMRA .set 0742Ch ; Group A Int MaskEVIMRB .set 0742Dh ; Group B Int MaskEVIMRC .set 0742Eh ; Group C Int MaskEVAIMRA .set 0742Ch ; Group A Int MaskEVAIMRB .set 0742Dh ; Group B Int MaskEVAIMRC .set 0742Eh ; Group C Int MaskIFRA  .set 0742fh ; Group A Int FlagIFRB  .set 07430h ; Group B Int FlagIFRC  .set 07431h ; Group C Int FlagEVIFRA .set 0742Fh ; Group A Int Flag EVIFRB .set 07430h ; Group B Int FlagEVIFRC .set 07431h ; Group C Int FlagEVAIFRA .set 0742Fh ; Group A Int Flag EVAIFRB .set 07430h ; Group B Int FlagEVAIFRC .set 07431h ; Group C Int FlagIVRA  .set 07432h ; Group A Int ID (x240 only)IVRB  .set 07433h ; Group B Int ID (x240 only)IVRC  .set 07434h ; Group C Int ID (x240 only)EVIVRA .set 07432h ; Group A Int ID (x240 only)EVIVRB .set 07433h ; Group B Int ID (x240 only)EVIVRC .set 07434h ; Group C Int ID (x240 only);Event Manager B (EVB) Registers (240x Only)GPTCONB .set 07500h ; General Timer ControlT3CNTB .set 07501h ; T1 CounterT3CMPB .set 07502h ; T1 Comp valueT3PERB .set 07503h ; T1 PeriodT3CONB .set 07504h ; T1 ControlT4CNTB .set 07505h ; T2 CounterT4CMPB .set 07506h ; T2 Comp valueT4PERB .set 07507h ; T2 PeriodT4CONB .set 07508h ; T2 ControlCOMCONB .set 07511h ; Compare ControlACTRB  .set 07513h ; Compare Output Action ControlDBTCONB .set 07515h ; Dead Band ControlCMPR4B .set 07517h ; Comp value 4CMPR5B .set 07518h ; Comp value 5CMPR6B .set 07519h ; Comp value 6CAPCONB .set 07520h ; Capture ControlCAPFIFOB  .set 07522h ; Capture FIFO4-6 StatusFIFO4B .set 07523h ; Capture 4 FIFO TopFIFO5B .set 07524h ; Capture 5 FIFO TopFIFO6B .set 07525h ; Capture 6 FIFO TopFIFOBT4B .set 07527h ; Capture 4 FIFO BottomFIFOBT5B .set 07528h ; Capture 5 FIFO BottomFIFOBT6B .set 07529h ; Capture 6 FIFO BottomIMRAB  .set 0752ch ; Group A Int MaskIMRBB  .set 0752dh ; Group B Int MaskIMRCB  .set 0752eh ; Group C Int MaskEVBIMRA .set 0752ch ; Group A Int MaskEVBIMRB .set 0752dh ; Group B Int MaskEVBIMRC .set 0752eh ; Group C Int MaskIFRAB  .set 0752fh ; Group A Int FlagIFRBB  .set 07530h ; Group B Int FlagIFRCB  .set 07531h ; Group C Int FlagEVBIFRA .set 0752fh ; Group A Int FlagEVBIFRB .set 07530h ; Group B Int FlagEVBIFRC .set 07531h ; Group C Int Flag;---------------------------------------------------------------------; Constant defines;---------------------------------------------------------------------B0_SADDR .set 00200h  ;Block B0 start addressB0_EADDR .set 002FFh  ;Block B0 end addressB1_SADDR .set 00300h  ;Block B1 start addressB1_EADDR .set 003FFh  ;Block B1 end addressB2_SADDR .set 00060h  ;Block B2 start addressB2_EADDR .set 0007Fh  ;Block B2 end address;Bit codes for Test bit instruction (BIT)BIT15  .set 0000h ;Bit Code for 15BIT14  .set 0001h ;Bit Code for 14BIT13  .set 0002h ;Bit Code for 13BIT12  .set 0003h ;Bit Code for 12BIT11  .set 0004h ;Bit Code for 11BIT10  .set 0005h ;Bit Code for 10BIT9  .set 0006h ;Bit Code for 9BIT8  .set 0007h ;Bit Code for 8BIT7  .set 0008h ;Bit Code for 7BIT6  .set 0009h ;Bit Code for 6BIT5  .set 000Ah ;Bit Code for 5BIT4  .set 000Bh ;Bit Code for 4BIT3  .set 000Ch ;Bit Code for 3BIT2  .set 000Dh ;Bit Code for 2BIT1  .set 000Eh ;Bit Code for 1BIT0  .set 000Fh ;Bit Code for 0; Used by the SBIT0 & SBIT1 MacroB15_MSK  .set 8000h ;Bit Mask for 15B14_MSK  .set 4000h ;Bit Mask for 14B13_MSK  .set 2000h ;Bit Mask for 13B12_MSK  .set 1000h ;Bit Mask for 12B11_MSK  .set 0800h ;Bit Mask for 11B10_MSK  .set 0400h ;Bit Mask for 10B9_MSK .set 0200h ;Bit Mask for 9B8_MSK .set 0100h ;Bit Mask for 8B7_MSK .set 0080h ;Bit Mask for 7B6_MSK .set 0040h ;Bit Mask for 6B5_MSK .set 0020h ;Bit Mask for 5B4_MSK .set 0010h ;Bit Mask for 4B3_MSK .set 0008h ;Bit Mask for 3B2_MSK .set 0004h ;Bit Mask for 2B1_MSK .set 0002h ;Bit Mask for 1B0_MSK .set 0001h ;Bit Mask for 0;External Data Space RegistersEXTDATA .set 8000h;---------------------------------------------------------------------; M A C R O - Definitions;---------------------------------------------------------------------SBIT0  .macro DMA,MASK ; Clear bit Macro  LACC DMA  AND #(0FFFFh-MASK)  SACL DMA      .endmSBIT1  .macro DMA,MASK ; Set bit Macro  LACC DMA  OR #MASK  SACL DMA       .endmKICK_DOG .macro   ;Watchdog reset macro  LDP #WD_KEY>>7  SPLK #05555h,WD_KEY  SPLK #0AAAAh,WD_KEY       .endmPOINT_PG0 .macro  LDP #00h       .endm POINT_B0 .macro  LDP #04h       .endmPOINT_PF1 .macro  LDP #0E0h       .endmPOINT_PF2 .macro  LDP #0E1h       .endmPOINT_EV .macro  LDP #0E8h      .endmwd_rst_1 .set 055h ; watchdog timer reset stringwd_rst_2 .set 0aah ; watchdog timer reset string