基于VHDL的SRAM 的读写访问程序

本文中的SRAM 指ISSI公司的IS61LV25616 ,本问中读数据采用简单的地址控制方法.写采用SRAM标准的写时序.

说明:

软件规划如下: 采用VHDL作为设计输入语言!

内部控制端口:地址输入[17:0]

数据输入[15:0]

读写信号R/W#, 高电平表示读信号,低电平表示写信号

数据输出[15:0]

SRAM 接口 : 地址输出[17:0]

双向数据总线[15:0]

片选CE#

读OE#

写WE#

LB#,UB# 一直有效

FOR EXAMPLE:

--*******************************************************************************

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--********************************************************************************

ENTITY DRI_SRAM IS

PORT

(

CLK: IN STD_LOGIC;

RST: IN STD_LOGIC;

--*********************************************************************************

DRI_Addr:IN STD_LOGIC_VECTOR(17 DOWNTO 0);

Write_Data:IN STD_LOGIC_VECTOR(15 DOWNTO 0);

Rd_Wr : IN STD_LOGIC;

Read_Data: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

--**********************************************************************************

SRAM_Addr: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);

DATA: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

CE# : OUT STD_LOGIC;

OE# : OUT STD_LOGIC;

WE#: OUTSTD_LOGIC;

LB#: OUT STD_LOGIC;

UB# :OUTSTD_LOGIC

--***********************************************************************************

);

END DRI_SRAM ;

ARCHITECTURE ARCH_DIR_SRAM OF DRI_SRAM IS

BEGIN

SIGNAL STATE: STD_LOGIC_VECTOR(4 DOWNTO 0);

SIGNAL CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);

PROCESS(CLK,RST)

BEGIN

IF (RST='1') THEN

Read_Data<=(OTHERS=>'0');

SRAM_Addr<=(OTHERS=>'0');

STATE<=(OTHERS=>'0')

DATA<=(OTHERS=>'Z');

CE#<='1';

OE#<='1';

WE#<='1';

LB#<='1';

UB#<='1';

ELSIF CLK'EVENT AND CLK='1' THEN

IF (STATE="00000") THEN

IF (Rd_Wr='1')THEN --*******从SRAM取数据

STATE<="00001";

ELSE

STATE<="10000";

END IF;

--**************读操作******************************************

ELSIF (STATE="00001") THEN

CE#<='0';

OE#<='0';

UB#<='0';

LB#<='0';

SRAM_Addr<=DRI_Addr;

STATE<="00010";

ELSIF (STATE="00010") THEN --****一个时周50ns

Read_Data<=Data;

STATE<="00011";

ELSIF (STATE="00011") THEN

CE#<='1';

OE#<='1';

UB#<='1';

LB#<='1';

STATE<="00000";

---******************写操作,由WE#控制写操作**************************************

ELSIF (STATE="10000") THEN

OE#<='1';

CE#<='0';

UB#<='0';

LB#<='0';

WE#<='1';

SRAM_Addr<=DRI_Addr;

DATA<=Write_Data;

STATE<="10010";

ELSIF (STATE="10010") THEN

WE#<='0';

STATE<="10011";

ELSIF (STATE="10011") THEN

WE#<='1';

CE#<='1';

UB#<='1';

LB#<='1';

STATE<="00000";

ELSE

STATE<=(OTHERS=>'0')

DATA<=(OTHERS=>'Z');

CE#<='1';

OE#<='1';

WE#<='1';

LB#<='1';

UB#<='1';

END IF;

END PROCESS;

END ARCH_DRI_SRAM;